Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produces devices with 250 nm, 180 nm, and 65 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The smaller sizes, however, mean device elements have to work closer together which can increase the chances of electrical interference, including cross-talk and parasitic capacitance.
To reduce the degree of electrical interference, dielectric insulating materials are used to fill the gaps, trenches, and other spaces between the device elements, metal lines, and other device features. The dielectric materials are chosen for their ease of formation in the spaces between device features, and their low dielectric constants (i.e., “k-values”). Dielectrics with lower k-values are better at minimizing cross-talk and RC time delays, as well as reducing the overall power consumption of the device. Conventional dielectric materials include silicon oxide, which has an average k-value between 4.0 and 4.2 when deposited with conventional CVD techniques.
During the formation of semiconductor devices, silicon nitride dielectric films have been used as barriers or etch stop layers in various applications. Silicon nitride dielectric films have etch rates different from those of silicon oxide such as low-k dielectric materials. Silicon nitride dielectric films may provide a desired protection for structure such as transistor gates lying thereunder.
However, the thickness non-uniformity of a silicon nitride dielectric film formed across a wafer having dense and isolated devices may be undesired. Further, the thickness of a silicon nitride dielectric film formed on a bottom, sidewall and top of a step-height profile may also adversely affect the gap-filling effect of a subsequent low-k dielectric material. The situation becomes even worse when semiconductor device geometries are scaling down.